Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering or covered by a heat-conducting lid. The die includes functional features, such as memory cells, processor circuits, and/or imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
Semiconductor manufacturers continually reduce the size of die packages to fit within the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the functional capacity of a semiconductor package without substantially increasing the surface area covered thereby (i.e., the package's “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be interconnected by electrically coupling the bond pads of the individual dies with the bond pads of adjacent dies using through-silicon vias (TSVs).
In vertically stacked packages the heat generated by the numerous dies in a small area, together with the height of the die stack, can make thermal management challenging. One approach to thermal management for semiconductor packages with heat-generating die stacks has been to provide a thermally conductive lid attached to both the die stack (for better thermal conduction) and the substrate (for better mechanical stability and die protection). Such lids can either be one-part lids (e.g., with a recess provided for the die stack) or multi-part lids (e.g., with an annular lower lid surrounding the die stack and connecting a planar upper lid to the substrate). Annular lower lids can be expensive to fabricate, and contribute little to the thermal management of the package device (e.g., as most heat is generated in the die stack and conducted vertically to the upper lid). Nevertheless, annular lower lids account for a significant portion of the total volume of the semiconductor package. Accordingly, there is a need for semiconductor packages with better thermal management solutions and more efficient use of space.